The data contents of memory systems are often protected in such a way that a plurality of redundant bits are additionally co-stored under the address of a data word. These bits are called check bits, K-bits or ECC-bits and arise by forming the parity sum over specific parts of the data word, which is usually referred to as EDC coding ("EDC" abbreviated for Error Detection Code). Upon readout of the memory word, the sub-parities are formed anew and compared to the allocated K-bits that are likewise readout. When there is equality for all K-bits, then it is concluded that the readout data word is error-free. Given inequality, conclusions about the kind of error are drawn from the pattern of the non-coincidence, what is referred to as the syndrome pattern.
Those K-bit positions that do not agree in said comparison are called syndromes. Specific syndrome patterns are decoded and the falsified bit position in the data word is thus potentially determined and corrected by inverting.
The formation of the K-bits (EDC encoding), the comparison of the K-bits, the decoding of the syndromes as well as the correction and potential alarm to a higher-ranking controller currently normally ensues with the assistance of specific controller modules, which are also referred to as EDC controllers below.
When a fault is then present in the memory system that causes an uncorrectable error, that is, a multi-bit error (for example, drive error or memory bit falsification error or memory module failure), this error can in fact be recognized by the error monitoring system with high probability, but only after the readout of the faulty data. This can be very late after the occurrence of the error under certain circumstances. The negative effects of the error can already be considerable at this late point in time.